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74lvt16374a 3.3v lvt 16-bit edge-triggered d-type flip-flop (3-state) product data sheet supersedes data of 2002 nov 01 2004 sep 16 integrated circuits
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2 2004 sep 16 features ? 16-bit edge-triggered flip-flop ? 3-state buffers ? output capability: +64 ma/32 ma ? ttl input and output switching levels ? input and output interface capability to systems at 5 v supply ? bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs ? live insertion/extraction permitted ? power-up reset ? power-up 3-state ? no bus current loading when output is tied to 5 v bus ? latch-up protection exceeds 500 ma per jedec std 17 ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model description the 74lvt16374a is a high-performance bicmos product designed for v cc operation at 3.3 v. this device is a 16-bit edge-triggered d-type flip-flop featuring non-inverting 3-state outputs. the device can be used as two 8-bit flip-flops or one 16-bit flip-flop. on the positive transition of the clock (cp), the q outputs of the flip-flop take on the logic levels set up at the d inputs. quick reference data symbol parameter conditions t amb = 25 c typical unit t plh t phl propagation delay ncp to nqx c l = 50 pf; v cc = 3.3 v 2.9 ns c in input capacitance v i = 0 v or 3.0 v 3 pf c out output pin capacitance outputs disabled; v o = 0 v or 3.0 v 9 pf i ccz total supply current outputs disabled; v cc = 3.6 v 70 m a ordering information type number package name description temperature range ( c) version 74lvt16374adl ssop48 plastic shrink small outline package; 48 leads; body width 7.5 mm 40 to +85 sot370-1 74lvt16374adgg tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm 40 to +85 sot362-1 74LVT16374AEV vfbga56 plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 7 0.65 mm 40 to +85 sot702-1
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 3 logic symbol (ssop and tssop packages) 3 2 1q0 1q1 1q2 6 5 1q3 47 46 44 43 1d0 1d1 1d2 1d3 48 1 9 8 1q4 1q5 1q6 12 11 1q7 41 40 38 37 1d4 1d5 1d6 1d7 1cp 1oe 14 13 17 16 36 35 33 32 25 24 20 19 23 22 30 29 27 26 2q0 2q1 2q2 2q3 2d0 2d21 2d2 2d3 2q4 2q5 2q6 2q7 2d4 2d5 2d6 2d7 2cp 2oe sw00018 logic symbol (ieee/iec) 48 1en 1 ? 46 44 43 41 40 38 37 36 c1 2en c2 2 ? 1 24 25 47 35 33 32 30 29 27 26 3 2 5 6 8 9 11 12 13 14 16 17 19 20 22 23 sw00016 1oe 1cp 2oe 2cp 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d1 2d2 2d3 2d4 2d5 2d6 2d7 1q1 1q2 1q3 1q4 1q5 1q6 1q7 2q1 2q2 2q3 2q4 2q5 2q6 2q7 1d 2d 1d0 2d0 1q0 2q0 pin configuration (ssop and tssop package options) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1oe 1q0 !q1 gnd 1q2 1q3 1q4 1q5 gnd 1q6 1q7 2q0 2q1 gnd 2q3 v cc 2q4 v cc 2q2 2q5 gnd 2q7 2oe 2q6 1cp 1d0 1d1 gnd 1d2 1d3 1d4 1d5 gnd 1d6 1d7 2d0 2d1 gnd 2d3 v cc 2d4 v cc 2d2 2d5 gnd 2d7 2cp 2d6 sw00017
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 4 pin description (ssop and tssop package options) pin number symbol function 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26 1d0 to 1d7 2d0 to 2d7 data inputs 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 1q0 to 1q7 2q0 to 2q7 data outputs 1, 24 1oe , 2oe output enable inputs (active-low) 48, 25 1cp, 2cp clock pulse inputs (active rising edge) 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0 v) 7, 18, 31, 42 v cc positive supply voltage ev package terminal placement, top view sr0243 123456 a b c d g h j k e f terminal assignments for 74lvt16374a in vfbga 1 2 3 4 5 6 a 1oe nc nc nc nc 1cp b 1q1 1q0 gnd gnd 1d0 1d1 c 1q3 1q2 vcc vcc 1d2 1d3 d 1q5 1q4 gnd gnd 1d4 1d5 e 1q7 1q6 1d6 1d7 f 2q0 2q1 2d1 2d0 g 2q2 2q3 gnd gnd 2d3 2d2 h 2q4 2q5 vcc vcc 2d5 2d4 j 2q6 2q7 gnd gnd 2d7 2d6 k 2oe nc nc nc nc 2cp function table inputs internal outputs operating mode noe ncp ndx register nq0 to nq7 operating mode l l l h l h l h load and read register l x nc nc hold h h x ndx nc ndx z z disable outputs h = high voltage level h = high voltage level one set-up time prior to the high-to-low e transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low e transition nc= no change x = don't care z = high-impedance aoffo state = low-to-high clock transition = not a low-to-high clock transition
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 5 logic diagram cp q d nd0 nq0 cp q d nd1 cp q d nd2 cp q d nd3 cp q d nd4 cp q d nd5 cp q d nd6 cp q d nd7 nq1 nq2 nq3 nq4 nq5 nq6 nq7 ncp noe sw00019 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +4.6 v i ik dc input diode current v i < 0 v 50 ma v i dc input voltage 3 0.5 to +7.0 v i ok dc output diode current v o < 0 v 50 ma v out dc output voltage 3 output in off or high state 0.5 to +7.0 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v v ih high-level input voltage 2.0 v v il input voltage 0.8 v i oh high-level output current 32 ma i o low-level output current 32 ma i ol low-level output current; current duty cycle 50 %; f 1 khz 64 ma d t/ d v input transition rise or fall rate; outputs enabled 10 ns/v t amb operating free-air temperature range 40 +85 c
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 6 dc electrical characteristics limits symbol parameter test conditions temp = 40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 2.7 v; i ik = 18 ma 0.85 1.2 v v cc = 2.7 to 3.6 v; i oh = 100 m a v cc 0.2 v cc v oh high-level output voltage v cc = 2.7 v; i oh = 8 ma 2.4 2.5 v v cc = 3.0 v; i oh = 32 ma 2.0 2.3 v cc = 2.7 v; i ol = 100 ma 0.07 0.2 v cc = 2.7 v; i ol = 24 ma 0.3 0.5 v ol low-level output voltage v cc = 3.0 v; i ol = 16 ma 0.25 0.4 v v cc = 3.0 v; i ol = 32 ma 0.3 0.5 v cc = 3.0 v; i ol = 64 ma 0.4 0.55 v rst power-up output low voltage 5 v cc = 3.6 v; i o = 1 ma; v i = gnd or v cc 0.1 0.55 v v cc = 3.6 v; v i = v cc or gnd control pins 0.1 1 i in p ut leakage current v cc = 0 v or 3.6 v; v i = 5.5 v 0.4 10 m a i i inp u t leakage c u rrent v cc = 3.6 v; v i = v cc data p ins 4 0.1 1 m a v cc = 3.6 v; v i = 0 v data pins 4 0.4 5 i off output off current v cc = 0 v; v i or v o = 0 v to 4.5 v 0.1 100 m a 7 v cc = 3 v; v i = 0.8 v 75 135 i hold bus hold current d inputs 7 v cc = 3 v; v i = 2.0 v 75 135 m a v cc = 0 v to 3.6 v; v cc = 3.6 v 500 i ex current into an output in the high state when v o > v cc v o = 5.5 v; v cc = 3.0 v 50 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2 v; v o = 0.5 v to v cc ; v i = gnd or v cc ; oe/oe = don't care 1 100 m a i ozh 3-state output high current v cc = 3.6 v; v o = 3.0 v; v i = v ih or v il 0.5 5 m a i ozl 3-state output low current v cc = 3.6 v; v o = 0.5 v; v i = v ih or v il 0.5 5 m a i cch v cc = 3.6 v; outputs high, v i = gnd or v cc, i o = 0 ma 0.07 0.12 i ccl quiescent supply current v cc = 3.6 v; outputs low, v i = gnd or v cc, i o = 0 ma 4 6 ma i ccz v cc = 3.6 v; outputs disabled; v i = gnd or v cc ; i o = 0 ma 6 0.07 0.12 d i cc additional supply current per input pin 2 v cc = 3 v to 3.6 v; one input at v cc 0.6 v, other inputs at v cc or gnd 0.1 0.2 ma notes: 1. all typical values are at v cc = 3.3 v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10msec. from v cc = 1.2 v to v cc = 3.3 v 0.3 v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 6. i ccz is measured with outputs pulled to v cc or gnd. 7. this is the bus hold overdrive current required to force the input to the opposite logic state.
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 7 ac characteristics gnd = 0 v; t r = t f = 2.5 ns; c l = 50 pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3 v 0.3 v v cc = 2.7 v unit min typ 1 max max f max maximum clock frequency 1 150 mhz t plh t phl propagation delay ncp to nqx 1 1.5 1.5 2.9 3.0 5.0 5.0 5.6 5.6 ns t pzh t pzl output enable time to high and low level 3 4 1.5 1.5 3.2 3.0 4.8 4.6 6.0 5.2 ns t phz t plz output disable time from high and low level 3 4 1.5 1.5 3.9 3.4 5.4 4.6 6.0 5.0 ns note: 1. all typical values are at v cc = 3.3 v and t amb = 25 c. ac setup requirements gnd = 0 v; t r = t f = 2.5 ns; c l = 50 pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3 v 0.3 v v cc = 2.7 v unit min typ min t s (h) t s (l) setup time ndx to ncp 2 2.0 2.0 0.7 0.7 2.0 2.0 ns t h (h) t h (l) hold time ndx to ncp 2 0.8 0.8 0 0 0.1 0.1 ns t w (h) tw(l) ncp pulse width high or low 1 1.5 3.0 0.6 1.6 1.5 3.0 ns ac waveforms v m = 1.5 v, v in = gnd to 3.0 v v m v m v m v m v m t w (h) t phl t plh ncp nqx sw00020 2.7 v 0 v v oh v ol 1/f max t w (l) waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency note: the shaded areas indicate when the input is permitted to change for predictable output performance. v m ndx v m v m v m v m ncp t s (h) t h (h) t s (l) t h (l) sw00021 v m 2.7 v 0 v 2.7 v 0 v waveform 2. data setup and hold times noe v m t pzh t phz 0 v nqx v m v m sw00014 2.7 v 0 v v oh 0.3 v v oh waveform 3. 3-state output enable time to high level and output disable time from high level noe t pzl t plz 0 v nqx v m v m v m sw00015 2.7 v 3 v v ol v ol +0.3 v waveform 4. 3-state output enable time to low level and output disable time from low level
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 8 test circuit and waveforms pulse generator r t v in d.u.t. v out c l r l v cc r l open v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0 v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0 v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5 v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. gnd 6 v sw00003 test circuit for 3-state outputs test switch t phz /t pzh gnd t plz /t pzl 6 v t plh /t phl open switch position input pulse requirements family amplitude rep. rate t w t r t f 74lvt16 2.7 v 10 mhz 500 ns 2.5 ns 2.5 ns
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 9 ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 10 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 11 vfbga56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm sot702-1
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 12 revision history rev date description _5 20040916 product data sheet (9397 750 14077). supersedes data of 2002 nov 01 (9397 750 10649). modifications: ? ac setup requirements table on page 7: v cc = 3.3 v 0.3 v change t s (h) and t s (l) setup time ndx to ncp min. from 2.5 ns to 2.0 ns change t h (h) and t h (l) hold time ndx to ncp min. from 0.5 ns to 0.8 ns v cc = 2.7 v change t s (h) and t s (l) setup time ndx to ncp min. from 2.5 ns to 2.0 ns change t h (h) and t h (l) hold time ndx to ncp min. from 0 ns to 0.1 ns _4 20021101 product data (9397 750 10649); supersedes product specification 74lvt16374a_3 of 1999 oct 18 (9397 750 06514) engineering change notice 8531781 29140 (date: 20021101)
philips semiconductors product data sheet 74lvt16374a 3.3v 16-bit edge-triggered d-type flip-flop (3-state) 2004 sep 16 13 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. published in the u.s.a. date of release: 09-04 document number: 9397 750 14077

data sheet status [1] objective data sheet preliminary data sheet product data sheet product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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